This invention relates to circuitry for applying reading, programming and erasing voltages to the wordlines of nonvolatile memory arrays and, therefore, to the control gates of nonvolatile memory cells such as floating-gate-type, electrically erasable programmable read-only-memory (EEPROM) cells.
This application discloses and claims circuitry that is related to the wordline driver circuitry described in U.S. Pat. No. 4,820,941, issued Apr. 11, 1989; in U.S. Pat. No. 4,823,318, issued Apr. 18, 1989; and in U.S. patent application Ser. No. 07/909,526, which is a continuation of 07/692,802, now abandoned, which is a continuation of abandoned 07/382,356, now abandoned, all of which are assigned to Texas Instruments Incorporated.
EEPROM arrays of the type used with the circuitry of this application are described, for example, in co-pending U.S. patent application Ser. No. 07/274,718, now abandoned, which is a continuation of 07/056,196, now abandoned, Ser. No. 07/494,051 (which is a continuation of 07/219,528, now abandoned, and which issued as U.S. Pat. No. 5,017,980 on May 21, 1991); and Ser. No. 07/494,042 (which is a continuation of 07/219,529, now abandoned, and which issued as U.S. Pat. No. 5,008,721 on Apr. 16, 1991) and Ser. No. 07/494,060 (which is a continuation of 07/219,530, now abandoned, and which issued as U.S. Pat. No. 5,012,307 on Apr. 30, 1991); each of those applications being assigned to Texas Instruments Incorporated. EEPROM arrays of the type described in the foregoing applications require circuitry that will switch as many as four different values of voltage to each wordline for the purposes of reading, programming and erasing information stored on the floating gates. One of those voltages, the erasing voltage, must be negative with respect to the array bitlines or cell source-drain regions.
The various EEPROM wordline voltages may be generated from the external supply voltage Vcc (approx. +5 V) using charge-pumped capacitors located on the memory chip. Circuits for switching from one positive voltage to a second positive voltage are well-known. For example, circuits for changing the wordline voltage from one value of positive voltage to another value of positive voltage, and even to reference voltage, have been used during the change from program mode to read mode of operation of electrically-programmable read-only-memories (EPROMs). However, in the case of EEPROMs, there is a need for improved circuits that will not only switch wordline reading and programming voltages, but that will also switch negative erasing voltages to a selected wordline. Switching of negative voltages presents a unique problem in that such circuits must be designed to prevent P-N junctions between the diffused areas and the substrate of such integrated circuits from becoming forward-biased during application of negative erase voltages.
In addition, there is a need for circuitry that will supply a third value of positive voltage to deselected wordlines during program mode operation and, therefore, that decreases the probability of disturbing the programmed status of deselected memory cells.
Generally, the field-effect transistors used to drive wordlines during programming and/or erasing of memory cells must have a longer channel length than that of the field-effect transistors used during reading of those memory cells. The longer channel-lengths are required to prevent "punch-through" between source and drain caused by the higher voltages used during programming and erasing. In general, transistors with longer channels have slower operating times than transistors with shorter channels. Because previous wordline driver circuits have used at least some of the same driver transistors for both read mode and for write and/or erase mode operations, the speed of operation during read mode operation has been limited by the required longer channel length of those same transistors.
Also generally, the field-effect transistors used to drive wordlines during programming and/or erasing of memory cells must have thicker gate insulation than that of the field-effect transistors used during reading of those memory cells. The thicker gate insulation is required to prevent "field-plate" or "gated-diode" electric-field breakdown between gate conductor and the substrate caused by the higher voltages used during programming and erasing.